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DRS4 Evaluation Board – Paul Scherrer Institut

Ever wanted to develop a Professional High Speed DAQ or a Storage Oscilloscope or even a High Speed Communications grade Logic Analyzer. Here is a front end Analog Mixed Chip with Eval Board.

You could make a High Speed Test Instrument and probably build a tablet app front end. How would a 200 M Hz Oscilloscope look on you 10 inch tablet. You will float in the clouds. – delabs

The DRS chip is a full custom Integrated Circuit developed at PSI, Switzerland. It contains a switched capacitor array (SCA) with 1024 cells, capable of digitizing eight analog signals with high speed (6 GSPS) and high accuracy (11.5 bit SNR) on a single chip.

DRS4 Evaluation Board - Paul Scherrer Institut
DRS4 Evaluation Board – Paul Scherrer Institut

By using channel cascading, we can configure this board with 2048 bins for each channel at the expense of a lower analog bandwidth of about 500 MHz. The on-board comparators enables the board to do a self-triggering on a programmed level of any of the input channels or logical combination of channels, much like an oscilloscope.

Highlights of Board with One DRS4 chip

  • Four 50-Ohm terminated input channels with SMA connectors
  • Active input buffers which result in an analog bandwidth of 700 MHz (-3dB).
  • One AD9245 ADC to digitize signals from the DRS4 chip
  • One Xilinx Spartan 3 FPGA for readout control
  • A 16-bit DAC to generate all on-board control voltages
  • A serial EEPROM containing serial number and calibration information
  • Internal trigger with user-defined thresholds on any of the four channes.

EE Journal – Embedded FPGA ASIC Design

Embedded Technology Journal and FPGA Structured ASIC Journal are now in EE Journal

EE Journal – Embedded FPGA ASIC Design

“The first year of a new publication is always exciting, but Embedded Technology Journal first year has been nothing short of stellar. We began, of course, with modest-sized audiences mulling our strange stories about putting tiny little computers into toasters and such. People pondered processors, studied software, meditated about memories, brushed up on busses, wrestled with RTOS, and fumbled with FPGAs. We covered applications ranging from smart phones to avionics and touched on some truly unique systems like golf radar and digital scarecrows.”

An approach to comprehensively verify a multi-clock design

An approach to comprehensively verify a multi-clock design

“One example of a combined solution is outlined in Figure 2, where timing exceptions between synchronous clocks are verified using Atrenta’s SpyGlass-TXV timing exception verification tool and the correct synchronization of interfaces between asynchronous clocks is handled by the SpyGlass-CDC tool, giving complete overall coverage.”