EE Journal – Embedded FPGA ASIC Design

Embedded Technology Journal and FPGA Structured ASIC Journal are now in EE Journal

EE Journal – Embedded FPGA ASIC Design

“The first year of a new publication is always exciting, but Embedded Technology Journal first year has been nothing short of stellar. We began, of course, with modest-sized audiences mulling our strange stories about putting tiny little computers into toasters and such. People pondered processors, studied software, meditated about memories, brushed up on busses, wrestled with RTOS, and fumbled with FPGAs. We covered applications ranging from smart phones to avionics and touched on some truly unique systems like golf radar and digital scarecrows.”

An approach to comprehensively verify a multi-clock design

An approach to comprehensively verify a multi-clock design

“One example of a combined solution is outlined in Figure 2, where timing exceptions between synchronous clocks are verified using Atrenta’s SpyGlass-TXV timing exception verification tool and the correct synchronization of interfaces between asynchronous clocks is handled by the SpyGlass-CDC tool, giving complete overall coverage.”

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