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	<title>delabs Technologies News &#187; ASIC EDA</title>
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		<title>Altera &#8211; FPGA CPLD and ASIC semiconductors</title>
		<link>http://www.delabs.net/news/2010/01/12/altera-fpga-cpld-and-asic-semiconductors/</link>
		<comments>http://www.delabs.net/news/2010/01/12/altera-fpga-cpld-and-asic-semiconductors/#comments</comments>
		<pubDate>Tue, 12 Jan 2010 09:22:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Embedded]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

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		<description><![CDATA[<p>Altera is one of the pioneers of Programmable Logic, following notable early leaders Signetics and MMI in introducing PLDs.</p>
<p>Interface with Twitter &#8211; @alteracorp &#8211; FPGA, CPLD and ASIC semiconductor devices.</p>
<p>Altera &#8211; FPGA CPLD and ASIC semiconductors</p>
]]></description>
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		<title>EDA and Product Design Ideas</title>
		<link>http://www.delabs.net/news/2009/11/27/eda-and-product-design-ideas/</link>
		<comments>http://www.delabs.net/news/2009/11/27/eda-and-product-design-ideas/#comments</comments>
		<pubDate>Fri, 27 Nov 2009 08:31:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Design]]></category>

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		<description><![CDATA[<p>Some Ideas of mine that were put in delabs Tweeter, related to EDA and Product Design</p>
<p>Product Design Optimization</p>
<p>Make Practical (it works), Affordable, Usable (ergonomics), Safe, Reliable (robust), Durable/Consistent &#38; Maintainable (Servicing) Products.</p>
<p>Dust and Contamination in Connectors</p>
<p>Once i opened a RF Millivolt Meter of Marconi Instruments. It did not have a spec of dust inside, not [...]]]></description>
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		<item>
		<title>the ASIC guy &#8211; Harry Gries &#8211; ASIC Methodology and EDA</title>
		<link>http://www.delabs.net/news/2009/06/20/the-asic-guy-harry-gries-asic-methodology-and-eda/</link>
		<comments>http://www.delabs.net/news/2009/06/20/the-asic-guy-harry-gries-asic-methodology-and-eda/#comments</comments>
		<pubDate>Sat, 20 Jun 2009 12:31:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

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		<description><![CDATA[<p>the ASIC guy &#8211; Harry Gries &#8211; ASIC Methodology and EDA</p>
<p>Harry Gries &#8211; ASIC Methodology and EDA Technology Consultant.</p>
<p>Harry&#8217;s Tweeter </p>
]]></description>
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		<slash:comments>0</slash:comments>
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		<item>
		<title>MathWorks Online Webinars</title>
		<link>http://www.delabs.net/news/2009/05/23/mathworks-online-webinars/</link>
		<comments>http://www.delabs.net/news/2009/05/23/mathworks-online-webinars/#comments</comments>
		<pubDate>Sat, 23 May 2009 16:09:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Software Tools]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

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		<description><![CDATA[<p>MathWorks Online Webinars</p>
<p>Design and Verify Control Systems using Simulink (Part 4): Real-Time Testing</p>
<p>Design and Verify Signal Processing and Communications Systems (Part 3): DSP Early Software Verification</p>
<p>MathWorks &#8211; leading global provider of software for technical computing and Model-Based Design.</p>
<p>MathWorks Webinars Tweeter</p>
]]></description>
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		<title>Functional verification at Brian Bailey Consulting</title>
		<link>http://www.delabs.net/news/2009/05/20/functional-verification-at-brian-bailey-consulting/</link>
		<comments>http://www.delabs.net/news/2009/05/20/functional-verification-at-brian-bailey-consulting/#comments</comments>
		<pubDate>Wed, 20 May 2009 07:10:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

		<guid isPermaLink="false">http://www.delabs.net/news/2009/05/20/functional-verification-at-brian-bailey-consulting/</guid>
		<description><![CDATA[<p>Functional verification at Brian Bailey Consulting</p>
<p>ESL and Verification guru &#8211; Business assessment and analysis, Competitive analysis and related Services.</p>
<p>Brian&#8217;s Tweets</p>
]]></description>
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		</item>
		<item>
		<title>GateRocket &#8211; Verification and Debug &#8211; FPGA</title>
		<link>http://www.delabs.net/news/2009/05/20/gaterocket-verification-and-debug-fpga/</link>
		<comments>http://www.delabs.net/news/2009/05/20/gaterocket-verification-and-debug-fpga/#comments</comments>
		<pubDate>Wed, 20 May 2009 05:47:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

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		<description><![CDATA[<p>GateRocket &#8211; Verification and Debug &#8211; FPGA</p>
<p>&#8220;GateRocket offers the industry&#8217;s first Device Native verification solution that enable companies to verify and debug their FPGA designs faster and with higher quality.&#8221;</p>
<p>RocketBlog &#8211; RocketTweet </p>
]]></description>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Cool Verification &#8211; Hardware verification EDA</title>
		<link>http://www.delabs.net/news/2009/05/19/cool-verification-hardware-verification-eda/</link>
		<comments>http://www.delabs.net/news/2009/05/19/cool-verification-hardware-verification-eda/#comments</comments>
		<pubDate>Tue, 19 May 2009 14:30:00 +0000</pubDate>
		<dc:creator>delabs</dc:creator>
				<category><![CDATA[ASIC EDA]]></category>
		<category><![CDATA[Tech-Tweeter]]></category>

		<guid isPermaLink="false">http://www.delabs.net/news/2009/05/19/cool-verification-hardware-verification-eda/</guid>
		<description><![CDATA[<p>Cool Verification &#8211; Hardware verification EDA</p>
<p>&#8220;Thoughts on hardware verification, the EDA industry, and related topics from the perspective of JL Gray, a verification consultant at Verilab.&#8221;</p>
<p>JL Gray &#8211; Twitter</p>
]]></description>
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