ASIC EDA (Page 2)

ASIC and EDA. DSP, FPGA and SOC.

MOSIS Is An Multi-Project Wafer (MPW) Integrated Circuit (IC) Fabrication Service Provider.

MOSIS – Affordable Integrated Circuits Fabrication

“MOSIS is operated by the Information Sciences Institute at the University of Southern California (USC). MOSIS merges multiple IC designs submitted by both companies and universities onto multi-project wafers (MPW) to share the cost of fabrication among multiple users.”

MOSIS - Affordable Integrated Circuits Fabrication

MOSIS – Metal Oxide Semiconductor Implementation Service

MOSIS keeps the cost of fabricating    prototype quantities low by aggregating multiple designs onto one mask set. This allows customers to share overhead costs associated with mask making, wafer fabrication, and assembly.

MOSIS Design Reference

A variety of design flows (digital, analog, mixed-signal) can be used with a number of different CAD tools, technology files, design kits, libraries and IP to create designs for processes accessed by MOSIS.

MOSIS Integrated Circuit Fabrication Service
USC Information Sciences Institute, 4676 Admiralty Way, 7th floor
Marina del Rey, CA 90292-6695, USA

Cadence RF Design Methodology Kit enables customers to rapidly address wireless opportunities by addressing system-level, verification and IC parasitic challenges.

Cadence Design Systems and OrCAD

Cadence Functional Verification Kit for ARM offers a comprehensive verification solution specifically for engineers developing ARM processor-based designs.

Cadence Design Systems and OrCAD

Cadence PSpice A/D and Advanced Analysis

Spice-based simulator for system design. It simulates complex mixed-signal designs containing both analog and digital parts, and it supports a wide range of simulation models such as IGBTs, pulse width modulators, DACs, and ADCs.

Cadence OrCAD Capture and Capture CIS 

Schematic design solution, supporting both flat and hierarchal designs from the simplest to the most complex. Seamless bi-directional integration with OrCAD PCB Editor enables data synchronization and cross-probing/placing between the schematic and the board design.

Cadence Tutorial for VLSI Design

This site contains a complete on-line tutorial for a typical bottom-up design flow using CADENCE Custom IC Design Tools (version 97A). The examples were generated using the HP 0.6 um CMOS14TB process technology files, prepared at North Carolina State University (NCSU) and made available through MOSIS.

TINA is an easy-to-use, but powerful, circuit simulation program based on a SPICE engine. TINA-TI is a fully functional version of TINA, loaded with a library of TI macromodels plus passive and active models.  TINA-TI’s new version 7.0 has changes from Version 6.0 in the following areas:

SPICE Analog Simulation Program TINA TI

SPICE Analog Simulation Program TINA TI

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages and waveforms. TINA’s schematic capture is truly intuitive-a real “quickstart.”

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The gEDA project is working on producing a full GPL’d suite of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production.

gEDA – Electronic Design Automation

Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout.

gEDA Project’s Homepage

gEDA - Electronic Design Automation

gschem is the schematic capture program/tool which is part of gEDA. Its sole purpose is to facilitate the graphical input of components/circuits.

PCB is an interactive printed circuit board editor. PCB offers high end features such as an autorouter and trace optimizer which can tremendously reduce layout time. For custom requirements,

GTKWave

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly.

GTKWave is a fully featured GTK+ based waveform viewer. GTKWave is designed to handle many signals at once, it has three signal searching modes (Regular Expressions, Hierarchy, and Tree) as well as the ability to display data in many different formats.