Verification-Testing

Leading Electronic Design Automation company. Provides solutions for design creation, simulation and verification. These aid the engineer in the creation of FPGA, ASIC, SoC and embedded systems.

Aldec – EDA and Design Verification

DO-254/CTS provides a single and automated environment to test all FPGA level requirements with full visibility and controllability at the FPGA pin level.

Features Include

  • At-speed testing in target devices
  • For use with Altera, Lattice, Mircrosemi and Xilinx
  • Automatic test vector generation
  • Hardware testing results visualization with waveform viewer

DO-254 FPGA Level In-Target Testing

Aldec DO-254 FPGA Level In-Target Testing

The FPGA testing results are captured at-speed and displayed using a simulator waveform viewer for advanced analysis and documentation.

Aldec Inc.
2260 Corporate Circle, Henderson, NV, 89074 USA.

Corelis offers a complete product line of JTAG (boundary-scan) circuit board testing tools for interconnect testing and JTAG in-system programming.

Corelis JTAG boundary-scan testing

Corelis also offers training classes on JTAG boundary-scan with hands-on lab exercises. Trainings covers all aspects of boundary-scan testing using Corelis ScanExpress tools. Design for testability (DFT), JTAG embedded functional test (JET), in-system programming (ISP) and test procedure generation are also covered.

The Blackhawk XDS560 Trace System

IEEE-1149.1 boundary-scan testing, In-System-Programming (ISP) of Flash memories and CPLDs and JTAG embedded testing.

The Blackhawk XDS560 Trace System combines a USB560m, LAN560, or PCI560 JTAG Emulator with a non-intrusive, hardware-based trace tool for debugging and profiling high-performance, DSP-based applications providing developers with advanced visibility to debug specialized problems that occur in high-performance, real-time embedded applications.